/**
 * @file    gt9881_i2c.h
 * @author  Giantec-Semi ATE
 * @brief   CMSIS GT98xx Device Peripheral Access Layer Header File
 * @version 0.1
 * 
 * @copyright Copyright (c) 2021 Giantec-Semi
 * 
 */

#ifndef GT98XX_DEVICE_GT9881_I2C_H_
#define GT98XX_DEVICE_GT9881_I2C_H_

#ifdef __cplusplus
  extern "C" {
#endif /* __cplusplus */

#include "gt9881.h"

/**
 * @addtogroup Peripheral_Registers_Structures
 * @{
 */
/**
 * @struct I2cTypedef
 * @brief I2C registers structure definition
 */
typedef struct tagI2cTypedef {
  __IO uint32_t IDREV;            ///< ID and Revision Register
       uint32_t RESERVED0[3];     ///< Reserved
  __IO uint32_t CFG;              ///< Configuration Register
  __IO uint32_t INTEN;            ///< Interrupt Enable Register
  __IO uint32_t STATUS;           ///< Status Register
  __IO uint32_t ADDR;             ///< Address Register
  __IO uint32_t DATA;             ///< Data Register
  __IO uint32_t CTRL;             ///< Control Register
  __IO uint32_t CMD;              ///< Command Register
  __IO uint32_t SETUP;            ///< Setup Register
} I2cTypedef;
/** @} Peripheral_Registers_Structures */

/**
 * @addtogroup Peripheral_Memory_Map
 * @{
 */
#define I2C1_BASE                 (PERIPH_BASE + 0x7000UL)      ///< I2C1 base address
#define I2C2_BASE                 (PERIPH_BASE + 0x8000UL)      ///< I2C2 base address
#define I2C3_BASE                 (PERIPH_BASE + 0x10000UL)     ///< I2C3 base address
/** @} Peripheral_Memory_Map */

/**
 * @addtogroup Peripheral_Declaration
 * @{
 */
#define I2C1                      ((I2cTypedef*)I2C1_BASE)      ///< I2C1 operator
#define I2C2                      ((I2cTypedef*)I2C2_BASE)      ///< I2C2 operator
#define I2C3                      ((I2cTypedef*)I2C3_BASE)      ///< I2C3 operator
/** @} Peripheral_Declaration */

/**
 * @defgroup I2C_Bitmap I2C Bitmap
 * @ingroup Peripheral_Registers_Bits_Definition
 * @brief Bitmap of I2C registers
 * @{
 */

#define I2C_IDREV_REVMINOR_Pos                  (0U)    ///< Position of I2C_IDREV_REVMINOR
#define I2C_IDREV_REVMINOR_Msk                  (0xFUL << I2C_IDREV_REVMINOR_Pos)   ///< Bitmask of I2C_IDREV_REVMINOR
/**
 * @def   I2C_IDREV_REVMINOR
 * @brief Minor revision number
 */
#define I2C_IDREV_REVMINOR                      I2C_IDREV_REVMINOR_Msk

#define I2C_IDREV_REVMAJOR_Pos                  (4U)    ///< Position of I2C_IDREV_REVMAJOR
#define I2C_IDREV_REVMAJOR_Msk                  (0xFFUL << I2C_IDREV_REVMAJOR_Pos)  ///< Bitmask of I2C_IDREV_REVMAJOR
/**
 * @def   I2C_IDREV_REVMAJOR
 * @brief Major revision number
 */
#define I2C_IDREV_REVMAJOR                      I2C_IDREV_REVMAJOR_Msk

#define I2C_IDREV_ID_Pos                        (12U)   ///< Position of I2C_IDREV_ID
#define I2C_IDREV_ID_Msk                        (0xFFFFFUL << I2C_IDREV_ID_Pos) ///< Bitmask of I2C_IDREV_ID
/**
 * @def   I2C_IDREV_ID
 * @brief ID number for IIC
 */
#define I2C_IDREV_ID                            I2C_IDREV_ID_Msk

#define I2C_CFG_FIFOSIZE_Pos                    (0U)    ///< Position of I2C_CFG_FIFOSIZE
#define I2C_CFG_FIFOSIZE_Msk                    (0x3UL << I2C_CFG_FIFOSIZE_Pos) ///< Bitmask of I2C_CFG_FIFOSIZE
/**
 * @def   I2C_CFG_FIFOSIZE
 * @brief FIFO size.
 * <pre>
 * @a 2'b00 : 2 bytes
 * @a 2'b01 : 4 bytes
 * @a 2'b10 : 8 bytes
 * @a 2'b11 : 16 bytes
 * </pre>
 */
#define I2C_CFG_FIFOSIZE                        I2C_CFG_FIFOSIZE_Msk

#define I2C_INTEN_FIFOEMPTY_Pos                 (0U)    ///< Position of I2C_INTEN_FIFOEMPTY
#define I2C_INTEN_FIFOEMPTY_Msk                 (0x1UL << I2C_INTEN_FIFOEMPTY_Pos)  ///< Bitmask of I2C_INTEN_FIFOEMPTY
/**
 * @def   I2C_INTEN_FIFOEMPTY
 * @brief Set to enable the FIFO Empty Interrupt
 */
#define I2C_INTEN_FIFOEMPTY                     I2C_INTEN_FIFOEMPTY_Msk

#define I2C_INTEN_FIFOFULL_Pos                  (1U)    ///< Position of I2C_INTEN_FIFOFULL
#define I2C_INTEN_FIFOFULL_Msk                  (0x1UL << I2C_INTEN_FIFOFULL_Pos)   ///< Bitmask of I2C_INTEN_FIFOFULL
/**
 * @def   I2C_INTEN_FIFOFULL
 * @brief Set to enable the FIFO Full Interrupt
 */
#define I2C_INTEN_FIFOFULL                      I2C_INTEN_FIFOFULL_Msk

#define I2C_INTEN_FIFOHALF_Pos                  (2U)    ///< Position of I2C_INTEN_FIFOHALF
#define I2C_INTEN_FIFOHALF_Msk                  (0x1UL << I2C_INTEN_FIFOHALF_Pos)   ///< Bitmask of I2C_INTEN_FIFOHALF
/**
 * @def   I2C_INTEN_FIFOHALF
 * @brief Set to enable the FIFO Half Interrupt.
 * <pre>
 * Receiver: Interrupts when the FIFO is half-full
 * Transmitter: Interrupts when the FIFO is half-empty
 * This interrupt depends on the transaction direction; don't enable this interrupt unless the transfer direction is determined, otherwise
 * </pre>
 */
#define I2C_INTEN_FIFOHALF                      I2C_INTEN_FIFOHALF_Msk

#define I2C_INTEN_ADDRHIT_Pos                   (3U)    ///< Position of I2C_INTEN_ADDRHIT
#define I2C_INTEN_ADDRHIT_Msk                   (0x1UL << I2C_INTEN_ADDRHIT_Pos)    ///< Bitmask of I2C_INTEN_ADDRHIT
/**
 * @def   I2C_INTEN_ADDRHIT
 * @brief Set to enable the Address Hit Interrupt.
 * <pre>
 * Master: interrupts when the addressed slave returned an ACK.
 * Slave: interrupts when the controller is addressed.
 * </pre>
 */
#define I2C_INTEN_ADDRHIT                       I2C_INTEN_ADDRHIT_Msk

#define I2C_INTEN_ARBLOSE_Pos                   (4U)    ///< Position of I2C_INTEN_ARBLOSE
#define I2C_INTEN_ARBLOSE_Msk                   (0x1UL << I2C_INTEN_ARBLOSE_Pos)    ///< Bitmask of I2C_INTEN_ARBLOSE
/**
 * @def   I2C_INTEN_ARBLOSE
 * @brief Set to enable the Arbitration Lose Interrupt.
 * <pre>
 * Master: interrupts when the controller loses the bus arbitration bus arbitration
 * Slave: not available in this mode
 * </pre>
 */
#define I2C_INTEN_ARBLOSE                       I2C_INTEN_ARBLOSE_Msk

#define I2C_INTEN_STOP_Pos                      (5U)    ///< Position of I2C_INTEN_STOP
#define I2C_INTEN_STOP_Msk                      (0x1UL << I2C_INTEN_STOP_Pos)   ///< Bitmask of I2C_INTEN_STOP
/**
 * @def   I2C_INTEN_STOP
 * @brief Set to enable the STOP Condition Interrupt.
 * <pre>
 * Interrupts when a STOP condition is detected.
 * </pre>
 */
#define I2C_INTEN_STOP                          I2C_INTEN_STOP_Msk

#define I2C_INTEN_START_Pos                     (6U)    ///< Position of I2C_INTEN_START
#define I2C_INTEN_START_Msk                     (0x1UL << I2C_INTEN_START_Pos)  ///< Bitmask of I2C_INTEN_START
/**
 * @def   I2C_INTEN_START
 * @brief Set to enable the START Condition Interrupt.
 * <pre>
 * Interrupts when a START condition/repeated START condition is detected.
 * </pre>
 */
#define I2C_INTEN_START                         I2C_INTEN_START_Msk

#define I2C_INTEN_BYTETRANS_Pos                 (7U)    ///< Position of I2C_INTEN_BYTETRANS
#define I2C_INTEN_BYTETRANS_Msk                 (0x1UL << I2C_INTEN_BYTETRANS_Pos)  ///< Bitmask of I2C_INTEN_BYTETRANS
/**
 * @def   I2C_INTEN_BYTETRANS
 * @brief Set to enable the Byte Transmit Interrupt.
 * <pre>
 * Interrupts when a byte of data is transmitted.
 * </pre>
 */
#define I2C_INTEN_BYTETRANS                     I2C_INTEN_BYTETRANS_Msk

#define I2C_INTEN_BYTERECV_Pos                  (8U)    ///< Position of I2C_INTEN_BYTERECV
#define I2C_INTEN_BYTERECV_Msk                  (0x1UL << I2C_INTEN_BYTERECV_Pos)   ///< Bitmask of I2C_INTEN_BYTERECV
/**
 * @def   I2C_INTEN_BYTERECV
 * @brief Set to enable the Byte Receive Interrupt.
 * <pre>
 * Interrupts when a byte of data is received Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually.
 * </pre>
 */
#define I2C_INTEN_BYTERECV                      I2C_INTEN_BYTERECV_Msk

#define I2C_INTEN_CMPL_Pos                      (9U)    ///< Position of I2C_INTEN_CMPL
#define I2C_INTEN_CMPL_Msk                      (0x1UL << I2C_INTEN_CMPL_Pos)   ///< Bitmask of I2C_INTEN_CMPL
/**
 * @def   I2C_INTEN_CMPL
 * @brief Set to enable the Completion Interrupt.
 * <pre>
 * Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration.
 * </pre>
 */
#define I2C_INTEN_CMPL                          I2C_INTEN_CMPL_Msk

#define I2C_STATUS_FIFOEMPTY_Pos                (0U)    ///< Position of I2C_STATUS_FIFOEMPTY
#define I2C_STATUS_FIFOEMPTY_Msk                (0x1UL << I2C_STATUS_FIFOEMPTY_Pos) ///< Bitmask of I2C_STATUS_FIFOEMPTY
/**
 * @def   I2C_STATUS_FIFOEMPTY
 * @brief Indicates that the FIFO is empty.
 */
#define I2C_STATUS_FIFOEMPTY                    I2C_STATUS_FIFOEMPTY_Msk

#define I2C_STATUS_FIFOFULL_Pos                 (1U)    ///< Position of I2C_STATUS_FIFOFULL
#define I2C_STATUS_FIFOFULL_Msk                 (0x1UL << I2C_STATUS_FIFOFULL_Pos)  ///< Bitmask of I2C_STATUS_FIFOFULL
/**
 * @def   I2C_STATUS_FIFOFULL
 * @brief Indicates that the FIFO is full.
 */
#define I2C_STATUS_FIFOFULL                     I2C_STATUS_FIFOFULL_Msk

#define I2C_STATUS_FIFOHALF_Pos                 (2U)    ///< Position of I2C_STATUS_FIFOHALF
#define I2C_STATUS_FIFOHALF_Msk                 (0x1UL << I2C_STATUS_FIFOHALF_Pos)  ///< Bitmask of I2C_STATUS_FIFOHALF
/**
 * @def   I2C_STATUS_FIFOHALF
 * @brief indicates that the FIFO is half
 * <pre>
 * Transmitter: Indicates that the FIFO is half-full.
 * Receiver: Indicates that the FIFO is half-empty.
 * </pre>
 */
#define I2C_STATUS_FIFOHALF                     I2C_STATUS_FIFOHALF_Msk

#define I2C_STATUS_ADDRHIT_Pos                  (3U)    ///< Position of I2C_STATUS_ADDRHIT
#define I2C_STATUS_ADDRHIT_Msk                  (0x1UL << I2C_STATUS_ADDRHIT_Pos)   ///< Bitmask of I2C_STATUS_ADDRHIT
/**
 * @def   I2C_STATUS_ADDRHIT
 * @brief Address Hit
 * <pre>
 * Master: indicates that a slave has responded to the transaction.
 * Slave: indicates that a transaction is targeting the controller (including the General Call).
 * </pre>
 */
#define I2C_STATUS_ADDRHIT                      I2C_STATUS_ADDRHIT_Msk

#define I2C_STATUS_ARBLOSE_Pos                  (4U)    ///< Position of I2C_STATUS_ARBLOSE
#define I2C_STATUS_ARBLOSE_Msk                  (0x1UL << I2C_STATUS_ARBLOSE_Pos)   ///< Bitmask of I2C_STATUS_ARBLOSE
/**
 * @def   I2C_STATUS_ARBLOSE
 * @brief Indicates that the controller has lost the bus arbitration (master mode only).
 */
#define I2C_STATUS_ARBLOSE                      I2C_STATUS_ARBLOSE_Msk

#define I2C_STATUS_STOP_Pos                     (5U)    ///< Position of I2C_STATUS_STOP
#define I2C_STATUS_STOP_Msk                     (0x1UL << I2C_STATUS_STOP_Pos)  ///< Bitmask of I2C_STATUS_STOP
/**
 * @def   I2C_STATUS_STOP
 * @brief Indicates that a STOP Condition has been transmitted/received.
 */
#define I2C_STATUS_STOP                         I2C_STATUS_STOP_Msk

#define I2C_STATUS_START_Pos                    (6U)    ///< Position of I2C_STATUS_START
#define I2C_STATUS_START_Msk                    (0x1UL << I2C_STATUS_START_Pos) ///< Bitmask of I2C_STATUS_START
/**
 * @def   I2C_STATUS_START
 * @brief Indicates that a START condition or a repeated START condition has been transmitted/received.
 */
#define I2C_STATUS_START                        I2C_STATUS_START_Msk

#define I2C_STATUS_BYTETRANS_Pos                (7U)    ///< Position of I2C_STATUS_BYTETRANS
#define I2C_STATUS_BYTETRANS_Msk                (0x1UL << I2C_STATUS_BYTETRANS_Pos) ///< Bitmask of I2C_STATUS_BYTETRANS
/**
 * @def   I2C_STATUS_BYTETRANS
 * @brief Indicates that a byte of data has been transmitted.
 */
#define I2C_STATUS_BYTETRANS                    I2C_STATUS_BYTETRANS_Msk

#define I2C_STATUS_BYTERECV_Pos                 (8U)    ///< Position of I2C_STATUS_BYTERECV
#define I2C_STATUS_BYTERECV_Msk                 (0x1UL << I2C_STATUS_BYTERECV_Pos)  ///< Bitmask of I2C_STATUS_BYTERECV
/**
 * @def   I2C_STATUS_BYTERECV
 * @brief Indicates that a byte of data has been received.
 */
#define I2C_STATUS_BYTERECV                     I2C_STATUS_BYTERECV_Msk

#define I2C_STATUS_CMPL_Pos                     (9U)    ///< Position of I2C_STATUS_CMPL
#define I2C_STATUS_CMPL_Msk                     (0x1UL << I2C_STATUS_CMPL_Pos)  ///< Bitmask of I2C_STATUS_CMPL
/**
 * @def   I2C_STATUS_CMPL
 * @brief Transaction Completion.
 * <pre>
 * Master: Indicates that a transaction has been issued fromthismaster andcompleted without losing the bus arbitration.
 * Slave: Indicates that a transaction addressing the controller has been completed.
 * This status bit must be cleared to receive the next transaction;
 * otherwise, the next incoming transaction will be blocked.
 * </pre>
 */
#define I2C_STATUS_CMPL                         I2C_STATUS_CMPL_Msk

#define I2C_STATUS_ACK_Pos                      (10U)   ///< Position of I2C_STATUS_ACK
#define I2C_STATUS_ACK_Msk                      (0x1UL << I2C_STATUS_ACK_Pos)   ///< Bitmask of I2C_STATUS_ACK
/**
 * @def   I2C_STATUS_ACK
 * @brief Indicates the type of the last.
 * <pre>
 * @a 1'b1 : ACK
 * @a 1'b0 : NACK
 * </pre>
 */
#define I2C_STATUS_ACK                          I2C_STATUS_ACK_Msk

#define I2C_STATUS_BUSBUSY_Pos                  (11U)   ///< Position of I2C_STATUS_BUSBUSY
#define I2C_STATUS_BUSBUSY_Msk                  (0x1UL << I2C_STATUS_BUSBUSY_Pos)   ///< Bitmask of I2C_STATUS_BUSBUSY
/**
 * @def   I2C_STATUS_BUSBUSY
 * @brief Indicates that the bus is busy.
 * <pre>
 * The bus is busy when a START condition is on bus and it ends when a STOP condition
 * @a 1'b1 : Busy
 * @a 1'b0 : Not busy
 * </pre>
 */
#define I2C_STATUS_BUSBUSY                      I2C_STATUS_BUSBUSY_Msk

#define I2C_STATUS_GENCALL_Pos                  (12U)   ///< Position of I2C_STATUS_GENCALL
#define I2C_STATUS_GENCALL_Msk                  (0x1UL << I2C_STATUS_GENCALL_Pos)   ///< Bitmask of I2C_STATUS_GENCALL
/**
 * @def   I2C_STATUS_GENCALL
 * @brief Indicates that the address of the current transaction is a general call address.
 * <pre>
 * This status is only valid in slave mode.
 * @a 1'b1 : General call
 * @a 1'b0 : Not general call
 * </pre>
 */
#define I2C_STATUS_GENCALL                      I2C_STATUS_GENCALL_Msk

#define I2C_STATUS_LINESCL_Pos                  (13U)   ///< Position of I2C_STATUS_LINESCL
#define I2C_STATUS_LINESCL_Msk                  (0x1UL << I2C_STATUS_LINESCL_Pos)   ///< Bitmask of I2C_STATUS_LINESCL
/**
 * @def   I2C_STATUS_LINESCL
 * @brief Indicates the current status of the SCL line on the bus.
 * <pre>
 * @a 1'b1 : High
 * @a 1'b0 : Low
 * </pre>
 */
#define I2C_STATUS_LINESCL                      I2C_STATUS_LINESCL_Msk

#define I2C_STATUS_LINESDA_Pos                  (14U)   ///< Position of I2C_STATUS_LINESDA
#define I2C_STATUS_LINESDA_Msk                  (0x1UL << I2C_STATUS_LINESDA_Pos)   ///< Bitmask of I2C_STATUS_LINESDA
/**
 * @def   I2C_STATUS_LINESDA
 * @brief Indicates the current status of the SDA line on the bus.
 * <pre>
 * @a 1'b1 : High
 * @a 1'b0 : Low
 * </pre>
 */
#define I2C_STATUS_LINESDA                      I2C_STATUS_LINESDA_Msk

#define I2C_ADDR_ADDR_Pos                       (0U)    ///< Position of I2C_ADDR_ADDR
#define I2C_ADDR_ADDR_Msk                       (0x3FFUL << I2C_ADDR_ADDR_Pos)  ///< Bitmask of I2C_ADDR_ADDR
/**
 * @def   I2C_ADDR_ADDR
 * @brief The slave address.
 * <pre>
 * For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid.
 * </pre>
 */
#define I2C_ADDR_ADDR                           I2C_ADDR_ADDR_Msk

#define I2C_DATA_DATA_Pos                       (0U)    ///< Position of I2C_DATA_DATA
#define I2C_DATA_DATA_Msk                       (0xFFUL << I2C_DATA_DATA_Pos)   ///< Bitmask of I2C_DATA_DATA
/**
 * @def   I2C_DATA_DATA
 * @brief I2C data
 * <pre>
 * Write this register to put one byte of data to the FIFO.
 * Read this register to get one byte of data from the FIFO.
 * </pre>
 */
#define I2C_DATA_DATA                           I2C_DATA_DATA_Msk

#define I2C_CTRL_DATACNT_Pos                    (0U)    ///< Position of I2C_CTRL_DATACNT
#define I2C_CTRL_DATACNT_Msk                    (0xFFUL << I2C_CTRL_DATACNT_Pos)    ///< Bitmask of I2C_CTRL_DATACNT
/**
 * @def   I2C_CTRL_DATACNT
 * @brief Data counts in bytes.
 * <pre>
 * Master: The number of bytes to transmit/receive. 0 means 256 bytes.
 * DataCnt will be decreased by one for each transmit/receive
 * Slave: the meaning of DataCnt depends on the DMA mode.
 * </pre>
 */
#define I2C_CTRL_DATACNT                        I2C_CTRL_DATACNT_Msk

#define I2C_CTRL_DIR_Pos                        (8U)    ///< Position of I2C_CTRL_DIR
#define I2C_CTRL_DIR_Msk                        (0x1UL << I2C_CTRL_DIR_Pos) ///< Bitmask of I2C_CTRL_DIR
/**
 * @def   I2C_CTRL_DIR
 * @brief Transaction direction.
 * <pre>
 * Master: Set this bit to determine the direction for the next transaction.
 * @a 1'b0 : Transmitter
 * @a 1'b1 : Receiver
 * Slave: The direction of the last received transaction.
 * @a 1'b0 : Receiver
 * @a 1'b1 : Transmitter
 * </pre>
 */
#define I2C_CTRL_DIR                            I2C_CTRL_DIR_Msk

#define I2C_CTRL_PHASESTOP_Pos                  (9U)    ///< Position of I2C_CTRL_PHASESTOP
#define I2C_CTRL_PHASESTOP_Msk                  (0x1UL << I2C_CTRL_PHASESTOP_Pos)   ///< Bitmask of I2C_CTRL_PHASESTOP
/**
 * @def   I2C_CTRL_PHASESTOP
 * @brief Enable this bit to send a STOP condition at the end of a transaction.
 * <pre>
 * Master mode only.
 * </pre>
 */
#define I2C_CTRL_PHASESTOP                      I2C_CTRL_PHASESTOP_Msk

#define I2C_CTRL_PHASEDATA_Pos                  (10U)   ///< Position of I2C_CTRL_PHASEDATA
#define I2C_CTRL_PHASEDATA_Msk                  (0x1UL << I2C_CTRL_PHASEDATA_Pos)   ///< Bitmask of I2C_CTRL_PHASEDATA
/**
 * @def   I2C_CTRL_PHASEDATA
 * @brief Enable this bit to send the data after Address Phase.
 * <pre>
 * Master mode only.
 * </pre>
 */
#define I2C_CTRL_PHASEDATA                      I2C_CTRL_PHASEDATA_Msk

#define I2C_CTRL_PHASEADDR_Pos                  (11U)   ///< Position of I2C_CTRL_PHASEADDR
#define I2C_CTRL_PHASEADDR_Msk                  (0x1UL << I2C_CTRL_PHASEADDR_Pos)   ///< Bitmask of I2C_CTRL_PHASEADDR
/**
 * @def   I2C_CTRL_PHASEADDR
 * @brief Enable this bit to send the address after START transaction.
 * <pre>
 * Master mode only.
 * </pre>
 */
#define I2C_CTRL_PHASEADDR                      I2C_CTRL_PHASEADDR_Msk

#define I2C_CTRL_PHASESTART_Pos                 (12U)   ///< Position of I2C_CTRL_PHASESTART
#define I2C_CTRL_PHASESTART_Msk                 (0x1UL << I2C_CTRL_PHASESTART_Pos)  ///< Bitmask of I2C_CTRL_PHASESTART
/**
 * @def   I2C_CTRL_PHASESTART
 * @brief Enable this bit to send a START condition at the beginning of transaction.
 * <pre>
 * Master mode only.
 * </pre>
 */
#define I2C_CTRL_PHASESTART                     I2C_CTRL_PHASESTART_Msk

#define I2C_CMD_CMD_Pos                         (0U)    ///< Position of I2C_CMD_CMD
#define I2C_CMD_CMD_Msk                         (0x7UL << I2C_CMD_CMD_Pos)  ///< Bitmask of I2C_CMD_CMD
/**
 * @def   I2C_CMD_CMD
 * @brief Write this register with the following values to perform the corresponding actions:
 * <pre>
 * @a 1'h0 : no action
 * @a 1'h1 : issue a data transaction (Master only)
 * @a 1'h2 : respond with an ACK to the received byte
 * @a 1'h3 : respond with a NACK to the received byte
 * @a 1'h4 : clear the FIFO
 * @a 1'h5 : reset the I2C controller (abort current transaction, set the SDA and SCL line to the
 *          open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty
 *          the FIFO.
 * </pre>
 */
#define I2C_CMD_CMD                             I2C_CMD_CMD_Msk

#define I2C_SETUP_IICEN_Pos                     (0U)    ///< Position of I2C_SETUP_IICEN
#define I2C_SETUP_IICEN_Msk                     (0x1UL << I2C_SETUP_IICEN_Pos)  ///< Bitmask of I2C_SETUP_IICEN
/**
 * @def   I2C_SETUP_IICEN
 * @brief Enable the IIC I2C controller.
 * <pre>
 * @a 1'b1 : Enable
 * @a 1'b0 : Disable
 * </pre>
 */
#define I2C_SETUP_IICEN                         I2C_SETUP_IICEN_Msk

#define I2C_SETUP_ADDRESSING_Pos                (1U)    ///< Position of I2C_SETUP_ADDRESSING
#define I2C_SETUP_ADDRESSING_Msk                (0x1UL << I2C_SETUP_ADDRESSING_Pos) ///< Bitmask of I2C_SETUP_ADDRESSING
/**
 * @def   I2C_SETUP_ADDRESSING
 * @brief I2C addressing mode.
 * <pre>
 * @a 1'b1 : 10-bit addressing mode
 * @a 1'b0 : 7-bit addressing mode
 * </pre>
 */
#define I2C_SETUP_ADDRESSING                    I2C_SETUP_ADDRESSING_Msk

#define I2C_SETUP_MASTER_Pos                    (2U)    ///< Position of I2C_SETUP_MASTER
#define I2C_SETUP_MASTER_Msk                    (0x1UL << I2C_SETUP_MASTER_Pos) ///< Bitmask of I2C_SETUP_MASTER
/**
 * @def   I2C_SETUP_MASTER
 * @brief Configure this device as a master or a slave.
 * <pre>
 * @a 1'b1 : Master mode
 * @a 1'b0 : Slave mode
 * </pre>
 */
#define I2C_SETUP_MASTER                        I2C_SETUP_MASTER_Msk

#define I2C_SETUP_DMAEN_Pos                     (3U)    ///< Position of I2C_SETUP_DMAEN
#define I2C_SETUP_DMAEN_Msk                     (0x1UL << I2C_SETUP_DMAEN_Pos)  ///< Bitmask of I2C_SETUP_DMAEN
/**
 * @def   I2C_SETUP_DMAEN
 * @brief Enable the direct memory access mode data transfer.
 * <pre>
 * @a 1'b1 : Enable
 * @a 1'b0 : Disable
 * </pre>
 */
#define I2C_SETUP_DMAEN                         I2C_SETUP_DMAEN_Msk

#define I2C_SETUP_TSCLHI_Pos                    (4U)    ///< Position of I2C_SETUP_TSCLHI
#define I2C_SETUP_TSCLHI_Msk                    (0x1FFUL << I2C_SETUP_TSCLHI_Pos)   ///< Bitmask of I2C_SETUP_TSCLHI
/**
 * @def   I2C_SETUP_TSCLHI
 * @brief The HIGH period of generated SCL clock is defined by T_SCLHi.
 * <pre>
 * SCL HIGH period = (4 + T_SP + T_SCLHi) * tpclk
 * The T_SCLHi value must be greater than T_SP and T_HDDAT values.
 * This field is only valid when the controller is in the master mode.
 * </pre>
 */
#define I2C_SETUP_TSCLHI                        I2C_SETUP_TSCLHI_Msk

#define I2C_SETUP_TSCLRATIO_Pos                 (13U)   ///< Position of I2C_SETUP_TSCLRATIO
#define I2C_SETUP_TSCLRATIO_Msk                 (0x1UL << I2C_SETUP_TSCLRATIO_Pos)  ///< Bitmask of I2C_SETUP_TSCLRATIO
/**
 * @def   I2C_SETUP_TSCLRATIO
 * @brief The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values.
 * <pre>
 * When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is
 * SCLLOWperiod = (4 + T_SP + T_SCLHi * ratio) * tpclk
 * @a 1'b1 : ratio = 2
 * @a 1'b0 : ratio = 1
 * This field is only valid when the controller is in the master mode.
 * </pre>
 */
#define I2C_SETUP_TSCLRATIO                     I2C_SETUP_TSCLRATIO_Msk

#define I2C_SETUP_THDDAT_Pos                    (16U)   ///< Position of I2C_SETUP_THDDAT
#define I2C_SETUP_THDDAT_Msk                    (0x1FUL << I2C_SETUP_THDDAT_Pos)    ///< Bitmask of I2C_SETUP_THDDAT
/**
 * @def   I2C_SETUP_THDDAT
 * @brief T_SUDAT defines the data hold time after SCL.
 * <pre>
 * Hold time = (4 + T_SP + T_HDDAT) * tpclk
 * </pre>
 */
#define I2C_SETUP_THDDAT                        I2C_SETUP_THDDAT_Msk

#define I2C_SETUP_TSP_Pos                       (21U)   ///< Position of I2C_SETUP_TSP
#define I2C_SETUP_TSP_Msk                       (0x7UL << I2C_SETUP_TSP_Pos)    ///< Bitmask of I2C_SETUP_TSP
/**
 * @def   I2C_SETUP_TSP
 * @brief T_SP defines the pulse width of spikes that must be suppressed by the input filter.
 * <pre>
 * Pulse width = T_SP * tpclk
 * </pre>
 */
#define I2C_SETUP_TSP                           I2C_SETUP_TSP_Msk

#define I2C_SETUP_TSUDAT_Pos                    (24U)   ///< Position of I2C_SETUP_TSUDAT
#define I2C_SETUP_TSUDAT_Msk                    (0x1FUL << I2C_SETUP_TSUDAT_Pos)    ///< Bitmask of I2C_SETUP_TSUDAT
/**
 * @def   I2C_SETUP_TSUDAT
 * @brief T_SUDAT defines the data setup time before releasing the SCL.
 * <pre>
 * Setup time = (4 + T_SP + T_SUDAT) * tpclk
 * tpclk = PCLK period
 * </pre>
 */
#define I2C_SETUP_TSUDAT                        I2C_SETUP_TSUDAT_Msk

/** @} I2C_BITMAP */

/**
 * @addtogroup Exported_Macros
 * @{
 */

/**
 * @def IS_I2C_ALL_INSTANCE
 * @brief Check if INSTANCE is SPI instance
 */
#define IS_I2C_ALL_INSTANCE(INSTANCE)           (((INSTANCE) == I2C1) || \
                                                 ((INSTANCE) == I2C2) || \
                                                 ((INSTANCE) == I2C3))

/** @} Exported_Macros */

#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif  /* GT98XX_DEVICE_GT9881_I2C_H_ */
